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? semiconductor components industries, llc, 2015 october, 2015 ? rev. 0 1 publication order number: kaf ? 16200/d kaf-16200 4500 (h) x 3600 (v) full frame ccd image sensor description the kaf ? 16200 is a single output, high performance ccd (charge coupled device) image sensor with 4500 (h) x 3600 (v) photoactive pixels designed for a wide range of color or monochrome image sensing applications. each pixel contains anti ? blooming protection by means of a lateral overflow drain thereby preventing image corruption during high light level conditions. each of the 6.0 m square pixels of the color version are selectively covered with red, green or blue pigmented filters for color separation. microlenses are added for improved sensitivity on both color and monochrome sensors. the sensor utilizes a transparent gate electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. table 1. general specifications parameter typical value architecture full frame ccd with square pixels total number of pixels 4641 (h) x 3695 (v) = 17.0 m number of effective pixels 4540 (h) x 3640 (v) = 16.5 m number of active pixels 4500 (h) x 3600 (v) = 16.2 m pixel size 6.0 m (h) x 6.0 m (v) active image size 27.0 mm (h) x 21.6 mm (v) 34.6 mm diag., aps ? h optical format aspect ratio 5:4 output sensitivity (q/v) 31 v/e ? charge capacity (24 mhz) 41 ke ? read noise (f = 24 mhz) 14 e ? rms dark current (60 c) 112 e ? /s dynamic range 69 db linear quantum efficiency (peak) color (600, 549, 480 nm) monochrome (540 nm) 33%, 40%, 33% 56% maximum frame rate 1.23 fps maximum data rate 24 mhz blooming protection 2000 x saturation exposure note: unless noted, all parameters are specified at 25 c. www.onsemi.com figure 1. kaf ? 16200 ccd image sensor features ? transparent gate electrode for high sensitivity ? high resolution, 35 mm diagonal format ? broad dynamic range ? low noise ? large image area applications ? astrophotography ? scientific imaging see detailed ordering and shipping information on page 2 of this data sheet. ordering information
kaf ? 16200 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kaf ? 16200 ? aba ? cd ? b1 monochrome, microlens, cerdip package, sealed clear cover glass with ar coating (both sides), grade 1 kaf ? 16200 ? aba serial number kaf ? 16200 ? aba ? cd ? b2 monochrome, microlens, cerdip package, sealed clear cover glass with ar coating (both sides), grade 2 kaf ? 16200 ? aba ? cd ? ae monochrome, microlens, cerdip package, sealed clear cover glass with ar coating (both sides), engineering grade kaf ? 16200 ? fxa ? cd ? b1 gen2 color (bayer rgb), special microlens, cerdip package, sealed clear cover glass with ar coating (both sides), grade 1 kaf ? 16200 ? fxa serial number kaf ? 16200 ? fxa ? cd ? b2 gen2 color (bayer rgb), special microlens, cerdip package, sealed clear cover glass with ar coating (both sides), grade 2 kaf ? 16200 ? fxa ? cd ? ae gen2 color (bayer rgb), special microlens, cerdip package, sealed clear cover glass with ar coating (both sides), engineering grade see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.
kaf ? 16200 www.onsemi.com 3 device description architecture figure 2. block diagram dark reference pixels surrounding the periphery of the device is a border of light shielded pixels creating a dark region. within this dark region are light shielded pixels that include 36 leading dark pixels on every line. there are also 30 full dark lines at the start and 23 full dark lines at the end of every frame. under normal circumstances, these pixels do not respond to light and may be used as a dark reference. dummy pixels within each horizontal shift register there are 20 leading additional shift phases 1 + 10 + 4 + 1 + 4 (see figure 2). these pixels are designated as dummy pixels and should not be used to determine a dark reference level. active buffer pixels forming the outer boundary of the effective active pixel region, there are 20 unshielded active buffer pixels between the photoactive area and the dark reference. these pixels are light sensitive but they are not tested for defects and non ? uniformities. for the leading 20 active column pixels, the first 4 pixels are covered with blue pigment while the remaining are arranged in a bayer pattern (r, gr, gb, b). cte monitor pixels two cte test columns, one on each of the leading and trailing ends and one cte test row are included for manufacturing test purposes. image acquisitio n an electronic representation of an image is formed when incident photons falling on the sensor plane create electron ? hole pairs within the device. these photon ? induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. the number of electrons collected is linearly dependent on light level and exposure time and non ? linearly dependent on wavelength. when the pixel?s capacity is reached, excess electrons are discharged into the lateral overflow drain to prevent crosstalk or ?blooming?. during the integration period, the v1 and v2 register clocks are held at a constant (low) level. charge transpor t the integrated charge from each photogate (pixel) is transported to the output using a two ? step process. each line (row) of charge is first transported from the vertical ccds to a horizontal ccd register using the v1 and v2 register clocks. the horizontal ccd is presented with a new line on the falling edge of v2 while h1 is held high. the horizontal ccds then transport each line, pixel by pixel, to the output structure by alternately clocking the h1 and h2 pins in a complementary fashion. a separate connection to the last h1 phase (h1l) is provided to improve the transfer speed of charge to the floating diffusion output amplifier. on each falling edge of h1l a new charge packet is dumped onto a floating diffusion and sensed by the output amplifier.
kaf ? 16200 www.onsemi.com 4 horizontal register output structure figure 3. output architecture (left or right) floating diffusion hccd charge transfer source follower #1 source follower #2 source follower #3 rd rg og h1l h1 h2 vdd vss voutx x= l or r note: represents either the left or the right output. the designation is omitted in the figure. the output consists of a floating diffusion capacitance connected to a three ? stage source follower. charge presented to the floating diffusion (fd) is converted into a voltage and is current amplified in order to drive off ? chip loads. the resulting voltage change seen at the output is linearly related to the amount of charge placed on the fd. once the signal has been sampled by the system electronics, the reset gate (rg) is clocked to remove the signal and fd is reset to the potential applied by reset drain (rd). increased signal at the floating diffusion reduces the voltage seen at the output pin. to activate the output structures, an off ? chip current source must be added to the vout pins of the device. see figure 4.
kaf ? 16200 www.onsemi.com 5 output load figure 4. recommended output structure load diagram 2n3904 or equiv. buffered video output iout = 5 ma vdd = +15 v 0.1 f vout 140 1 k note: component values may be revised based on operating conditions and other design considerations.
kaf ? 16200 www.onsemi.com 6 physical description pin description and device orientation figure 5. pinout diagram note: as viewed from the bottom. table 3. pinout pin name description 1 vsub substrate 2 h1last last horizontal phase 3 og output gate 4 rg reset gate 5 rd reset drain 6 vss amplifier return 7 vout video output 8 vdd amplifier supply 9 h2 horizontal phase 2 10 h1 horizontal phase 1 11 vsub substrate 12 vsub substrate 13 vsub substrate 14 h1 horizontal phase 1 15 h2 horizontal phase 2 16 vsub substrate pin name description 17 vsub substrate 18 lodb lateral overflow drain, bottom of die 19 v1 vertical phase 1 20 v1 vertical phase 1 21 v2 vertical phase 2 22 v2 vertical phase 2 23 lodt lateral overflow drain, top of die 24 vsub substrate 25 vsub substrate 26 lodt lateral overflow drain, top of die 27 v2 vertical phase 2 28 v2 vertical phase 2 29 v1 vertical phase 1 30 v1 vertical phase 1 31 lodb lateral overflow drain, bottom of die 32 vsub substrate
kaf ? 16200 www.onsemi.com 7 imaging performance table 4. typical operational conditions description condition notes readout time (t readout ) 652 ms includes overclock pixels integration time (t int ) varies per test: bright field 250 ms, dark field 1 sec, saturation 250 ms, low light 33 ms horizontal clock frequency 24 mhz temperature 25 c room temperature mode integrate ? readout cycle operation typical operating conditions table 5. specifications description symbol min nom. max units notes verification plan saturation signal ne ? sat 35 41 ke ? design 10 charge to voltage conversion q/v 31 v/e ? 1 design 10 quantum efficiency at peak red green blue qe max 33 40 33 % design 10 quantum efficiency at peak ? mono qe max 56 % design 10 photo response non-linearity (10 ? 90% nsat) prnl 4 10 % die 9 green difference (gr/gb) 2 % design 10 photo response non-uniformity prnu 10 25 %p ? p 2 die 9 dark current 50 pa/cm 2 3 die 9 dark signal non-uniformity dsnu 4 mv p ? p 5 die 9 dark signal doubling temperature t 4.7 c 11 design 10 read noise n r 14 e ? rms design 10 dynamic range dr 69.3 db 4 design 10 horizontal charge transfer efficiency hcte 0.999995 5 die 9 vertical charge transfer efficiency vcte 0.999999 0.999999 die 9 blooming protection x ab 2000 x v sat 6 design 10 dc offset, output amplifier v odc 7.7 v 7 die 9 output amplifier bandwidth f ? 3db 220 mhz design 10 output impedance, amplifier r out 132 die 9 reset feedthru v rft 0.5 v design 10 1. increasing output load currents to improve bandwidth will decrease the conversion factor (q/v). 2. difference between the maximum and minimum average signal levels of 168 168 blocks within the sensor on a per color basis as a % of average signal level. 3. t = 60 c and t int = 0, average non-illuminated signal with respect to over-clocked horizontal register signal. 4. 20log (ne ? sat / n r ). specified at t = 60 c. 5. measured per transfer above and below ( 70% v sat min) saturation exposure levels. typically, no degradation in hccd cte is observed up to 24 mhz. 6. x ab is the number of times above the v sat illumination level that the sensor will bloom by spot size doubling. the spot size is 10% of the imager height. x ab is measured at 4 ms. 7. video level offset with respect to ground. 8. total dark signal = (v dark,int * t int ) + v dark,read * t readout . 9. a parameter that is measured on every sensor during production testing. 10. a parameter that is quantified during the design verification activity. 11. this value is valid only near 25 c.
kaf ? 16200 www.onsemi.com 8 typical performance curves 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 400 500 600 700 800 900 1000 absolute quantum efficiency illumination wavelength (nm) figure 6. typical monochrome quantum efficiency 0 0.1 0.2 0.3 0.4 0.5 400 450 500 550 600 650 700 750 800 850 900 950 1000 absolute quantum efficiency illumination wavelength (nm) figure 7. typical color quantum efficiency
kaf ? 16200 www.onsemi.com 9 figure 8. typical green (red) ? green (blue) quantum efficiency difference ? 0.01 ? 0.005 0 0.005 0.01 0.015 0.02 400 500 600 700 800 900 1000 absolute qe difference lambda (nm) gr-gb figure 9. typical vertical angular dependance of quantum efficiency for monochrome devices 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 1015202530 vertical angle response angle blue light green light red light
kaf ? 16200 www.onsemi.com 10 figure 10. typical horizontal angular dependance of quantum efficiency for monochrome devices 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 1015202530 horizontal angle response angle blue light green light red light figure 11. typical vertical angular dependance of quantum efficiency for color devices 0 0.2 0.4 0.6 0.8 1 1.2 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 1015202530 vertical angle response angle
kaf ? 16200 www.onsemi.com 11 figure 12. typical horizontal angular dependance of quantum efficiency for color devices 0 0.2 0.4 0.6 0.8 1 1.2 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 1015202530 horizontal angle response angle 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0246810 x ab exposure time (ms) figure 13. typical anti-blooming performance: signal vs. exposure
kaf ? 16200 www.onsemi.com 12 figure 14. typical dark current performance vs. temperature 1 10 100 1000 34.5 35 35.5 36 36.5 37 37.5 38 dark current (e/sec) 1000 e/kbt integration dark current readout dark current figure 15. dark current doubling temperature dependence ? 30 ? 20 ? 1001020304050607080 2.00 3.00 4.00 5.00 6.00 7.00 temperature ( c) integration dark current doubling temperature ( c)
kaf ? 16200 www.onsemi.com 13 figure 16. typical linearity performance 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 0 20 40 60 80 100 120 140 signal (e) integration time (a.u) figure 17. typical non-linearity plot ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 0 1 2 3 4 5 6 0 10000 20000 30000 40000 50000 linearity error (%) signal (e) 10% 90%
kaf ? 16200 www.onsemi.com 14 defect definitions operating conditions bright defect tests performed at t = 25 c dark defect tests performed at t = 25 c table 6. specifications classification points clusters columns class 1 2,000 40 0 class 2 2,000 40 15 point defects a pixel that deviates by more than 9 mv above neighboring pixels under non ? illuminated conditions. ? or ? a pixel that deviates by more than 7% above or 11% below neighboring pixels under illuminated conditions. cluster defect a grouping of not more than 10 adjacent point defects. cluster defects are separated by no less than 4 good pixels in any direction. column defect a grouping of more than 10 point defects along a single column ? or ? a column that deviates by more than 1.2 mv above or below neighboring columns under non ? illuminated conditions. ? or ? a column that deviates by more than 1.5% above or below neighboring columns under illuminated conditions. column and cluster defects are separated by at least 4 good columns in the x direction. no multiple column defects (double or more) will be permitted. saturated columns a column that deviates by more than 100 mv above neighboring columns under non ? illuminated conditions. no saturated columns are allowed.
kaf ? 16200 www.onsemi.com 15 operation table 7. absolute maximum ratings description symbol minimum maximum units notes diode pin voltages v diode ?0.5 +20.0 v 1, 2 gate pin voltages v gate1 ? 14.3 +14.5 v 1, 3 reset gate pin voltages v rg ? 0.5 +14.5 v 1 overlapping gate voltages v 1 ? 2 ? 14.3 +14.5 v 4 non ? overlapping gate voltages v o ? o ? 14.3 +14.5 v 5 output bias current i out ? 30 ma 6 lod diode voltage v lod ? 0.5 +13.5 v 1 operating temperature t op 0 60 c 7 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. referenced to pin sub. 2. includes pins: rd, vdd, vss, vout. 3. includes pins: v1, v2, h1, h1l, h2, h2l, og. 4. voltage difference between overlapping gates. includes: v1 to v2, h1/h1l to h2, h1l to og, v1 to h2. 5. voltage difference between non ? overlapping gates. includes: v1 to h1/h1l. 6. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher cu rrents and lower load capacitance at the expense of reduced gain (sensitivity). operation at these values will reduce mttf (mean time to f ailure). 7. noise performance will degrade at higher temperatures. power ? up sequence the sequence chosen to perform an initial power ? up is not critical for device reliability. a coordinated sequence may minimize noise and the following sequence is recommended: 1. connect the ground pins (vsub). 2. supply the appropriate biases and clocks to the remaining pins. table 8. dc bias operating conditions description symbol minimum nominal maximum units notes reset drain rd 11.3 11.5 11.7 v output amplifier return vss 0.7 v output amplifier supply vdd 14.5 15.0 v substrate sub 0 v output gate og ? 2.3 ? 2.5 ? 2.7 v lateral drain/guard lod 10.8 11.0 11.2 v video output load current i out ? 5 ? 10 ma 1 1. an output load sink must be applied to each of the four vout pins to activate output amplifier ? see figure 4.
kaf ? 16200 www.onsemi.com 16 ac operating conditions table 9. clock levels description symbol level minimum nominal maximum units effective capacitance notes vertical ccd clock ? phase 1 v1 low ? 8.8 ? 9.0 ? 9.2 v 1, 2, 3 high 2.3 2.5 2.7 v vertical ccd clock ? phase 2 v2 low ? 8.8 ? 9.0 ? 9.2 v 1, 2, 3 high 3.3 3.5 3.7 v horizontal ccd clock ? phase 1 h1 low ? 3.8 ? 4.0 ? 4.2 v 1, 2, 3 high 1.8 2.0 2.2 v horizontal ccd clock ? phase 2 h2 low ? 3.8 ? 4.0 ? 4.2 v 1, 2, 3 high 1.8 2.0 2.2 v horizontal ccd clock ? phase 1 (last) h1l low ? 5.8 ? 6.0 ? 6.2 v 1, 2, 3 high 1.8 2.0 2.2 v reset gate rg low 0.8 1.0 1.2 v 1, 2, 3 high 7.8 8.0 8.2 v 1. all pins draw less than 10 a dc current. 2. capacitance values relative to sub (substrate). 3. capacitance values of left and right pins combined where appropriate.
kaf ? 16200 www.onsemi.com 17 timing table 10. requirements and characteristics description symbol minimum nominal maximum units notes h1, h2 clock frequency f h 24 mhz 1, 2 v1, v2 rise, fall times t v1r , t v1f 2 s v1 ? v2 cross ? over v vcr 0 1 2 v h1 ? h2 cross ? over v hcr ? 2 ? 1 0 v h1l rise ? h2 fall crossover v h1lcr ? 1 v vccd to hccd transfer t vh 5 s v1, v2 clock pulse width t v 8 s pixel period (1 count) t e 41.67 ns 2 line time t line 219 s readout time t readout 0.81 s 3 frame rate t frame 1.23 fps integration time t int 4 1. 50% duty cycle values. 2. cte will degrade above the nominal frequency. 3. t readout = t line * 3695 lines 4. integration time is user specified. edge alignment figure 18. detail of vertical clock timing v1 v2 tvhigh tvrise tvrise tvcross vvcr tvhigh tvhcte hccd clock tv-h = 2*tvhigh+2*tvrise+tvcross+tvhcte hccd clock the falling edge of v1 transfers charge between rows. the falling edge of v2 transfers the vccd charge packet from v2 into hccd phase h1. to allow for full charge transfer from the vccd to the hccd, a delay tv hcte is required between the falling edge of v2 and the start of hccd clocking.
kaf ? 16200 www.onsemi.com 18 frame timing row annotation: [row# transferred to hccd] : row assignment. row #3695 is the last row (optical injection). any overclock beyond that sends null values to the hccd. figure 19. frame timing kaf ? 16200 frame timing t int line 1:lod 2: dark#1 3 3694:dk#60 t readout the integration of dark and photo ? signal in the vccd is continuous, as there is no pixel reset mechanism. ?t int ? may refer to the time the vccd clocks are static, and therefore avoid image smear during readout. line timing figure 20. line timing v1 v2 h1 h2 kaf ? 16200 line timing t v t v t vhcte 4641 cnts t line 4641: no overclock of hccd pixel timing figure 21. pixel timing rg vout h1 h2
kaf ? 16200 www.onsemi.com 19 references for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kaf ? 16200 www.onsemi.com 20 mechanical information completed assembly figure 22. completed assembly drawing
kaf ? 16200 www.onsemi.com 21 cover glass specification 1. scratch and dig: 20 micron max 2. substrate material: schott d263t eco @ 1 mm thickness 3. multilayer anti ? reflective coating. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 kaf ? 16200/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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